59 ecc second address register - eccsar, Table 86. ecc second address register - eccsar, 59ecc second address register - eccsar – Intel CONTROLLERS 413808 User Manual
Page 199: 86 ecc second address register - eccsar, Ecc second address register, Ecc second address register - eccsar, Ecc second, Address register - eccsar, P_ad[31:0, Address translation unit (pci-x)—intel
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
199
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.14.59 ECC Second Address Register - ECCSAR
When the ECC Error Phase register (bits 6:4 of the ECCCSR) is non-zero (indicating
that an error has been captured) and the failing transaction included a dual address
cycle (DAC), the ECCSAR register indicates the contents of the
P_AD[31:0]
bus (for
64- and 32-bit buses) for the second address phase of the transaction that included the
error. When the ECC Error Phase register is zero, the contents of this register are
undefined.
Note:
Registers that store information from the failing transaction always store information
directly from the bus (uncorrected), even when correction of the error is possible.
Note:
The
“ECC Control and Status Register - ECCCSR”
“ECC Second Address Register - ECCSAR”
, and
report the actual transaction that has the error. For example, when the Split
Completion of an original Outbound Read request has an error, the information
regarding the Split Completion is reported.
Table 86. ECC Second Address Register - ECCSAR
Bit
Default
Description
31:00 0000 0000H
ECC Second Address - This register represents the most significant 32-bits of the address for a DAC
transaction.
Note:
When the failing transaction used a single address cycle (SAC), then the contents of this
register must be 0.
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+0E0H