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8 register definitions, Table 470. i2c register summary, 470 i – Intel CONTROLLERS 413808 User Manual

Page 714: Table 470. i, C register summary, The following registers are associated with the i, C bus interface units. each i

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Intel

®

413808 and 413812—I

2

C Bus Interface Units

Intel

®

413808 and 413812 I/O Controllers in TPER Mode

Developer’s Manual

October 2007

714

Order Number: 317805-001US

14.8

Register Definitions

The following registers are associated with the I

2

C Bus Interface Units. Each I

2

C Bus

Interface Unit has five memory-mapped control registers for independent operation. In

register titles, x is 0 or 1 for unit 0 or 1, respectively.
They are all located within the peripheral memory- mapped address space of the

4138xx.

Table 470. I

2

C Register Summary

Section, Register Name, Acronym, Page

Section 14.8.1, “I2C Control Register x — ICRx” on page 715

Section 14.8.2, “I2C Status Register x — ISRx” on page 717

Section 14.8.3, “I2C Slave Address Register x — ISARx” on page 719

Section 14.8.4, “I2C Data Buffer Register x — IDBRx” on page 720

Section 14.8.5, “I2C Bus Monitor Register x — IBMRx” on page 721

Section 14.8.6, “I2C Manual Bus Control Register x — IMBCRx” on page 722