Intel CONTROLLERS 413808 - Manual (Page 240)

Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
240 Order Number: 317805-001US
3.3.1.2 Inbound Memory Write Transaction
An inbound write transaction is initiated by a PCI Express requester and is targeted at
either 4138xx local memory or a 4138xx memory-mapped register.
Data flow for an inbound write transaction is summarized as:
• The ATU accepts the write transaction when the PCI address is within one of the
inbound translation windows defined by the ATU Inbound Base Address Register,
Inbound Upper Base Address Register, and Inbound Limit Register.
• When the IPHQ is full or the IPDQ overflows, a flow control error occurred and an
ERR_FATAL is returned to the root complex.
Once the inbound write packet has passed all the TLP validation checks, the ATUs
internal bus interface becomes aware of the inbound write. When there are additional
write transactions ahead in the IPHQ, the current transaction remains posted until
ordering and priority have been satisfied (Refer to Section 3.8.3 ) and the transaction is
attempted on the internal bus by the ATU internal master interface.
Data flow for the inbound write transaction on the internal bus is summarized as:
• The ATU internal bus master requests the internal bus when IPHQ has at least one
entry.
• When the internal bus is granted, the internal bus master interface initiates the
write transaction by driving the translated address onto the internal bus. For details
on inbound address translation, see Section 3.3, “ATU Address Translation” on
page 234 .
• When an internal bus target does not claim write transaction, a master abort
condition is signaled on the internal bus. The current transaction is flushed from the
queue and an unsupported request (UR) message may be generated on the PCI
Express interface.
• The ATU initiator interface attempts a 128-bit wide transfer on the internal bus.
When the target that claims the request does not support 128-bit wide transfers, a
64-bit wide transfer is used. Transfers use internal bus byte enables to mask the
bytes not written in each data phase. Write data is transferred from the IPDQ to the
internal bus while data is available and the internal bus interface retains internal
bus ownership. Refer to Section 7.0, “System Controller (SC) and Internal Bus
Bridge” for details of internal bus operation.
• The internal bus interface stops transferring data from the current transaction to
the internal bus when one of the following conditions becomes true:
— The internal bus initiator interface loses bus ownership.
— The data from the current transaction has completed (satisfaction of payload
length). An initiator termination is performed and the bus returns to idle.
— A Master Abort is signaled on the internal bus. Data is flushed from the IPDQ.