Intel CONTROLLERS 413808 - Manual (Page 19)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 19
Contents—Intel
®
413808 and 413812
16.5.7.3 Threshold Events .................................................................... 758
16.5.7.4 PCI Interface Events ............................................................... 759
16.5.7.5 PCI Express Interface Events.................................................... 760
16.5.7.6 North Internal Bus Events ........................................................ 761
16.5.7.7 South Internal Bus Events........................................................ 762
17.0 Clocking and Reset ................................................................................................... 763
17.1 Clocking Overview........................................................................................... 763
17.1.1 Clocking Theory of Operation ................................................................. 764
17.1.1.1 Clocking Region 1 (PCI Express) ............................................... 764
17.1.1.2 Clocking Region 2 (PCI)........................................................... 764
17.1.1.2.1 Central Resource Mode (PCIX_EP# = ‘1’) ........................765
17.1.1.2.2 cPCI Hot-Swap Mode (PCIX_EP# = ‘0’ and HS_SM# = ‘0’) ...
766
17.1.1.2.3 End Point Mode (PCIX_EP# = 0 and HS_SM# = 1).......... 766
17.1.1.2.4 Secondary Clock Outputs..................................................767
17.1.1.3 Clocking Region 3 (Internal Bus)............................................... 768
17.1.1.4 Clocking Region 4 (Peripheral Bus Interface) .............................. 768
17.1.1.5 Clocking Region 5 ................................................................... 768
17.1.1.6 Clocking Region 7 (Intel XScale
®
Processor)............................... 768
17.1.2 Clocking Region Summary..................................................................... 769
17.2 Reset Overview............................................................................................... 770
17.2.1 Fundamental Reset............................................................................... 770
17.2.2 Software Reset .................................................................................... 771
17.2.3 Secondary Bus Reset ............................................................................ 771
17.2.4 PCI Reset............................................................................................ 772
17.2.5 PCI Express Hot Reset .......................................................................... 772
17.2.6 WARM_RST# Reset Mechanism.............................................................. 772
17.2.7 Intel XScale
®
Processor Reset Mechanism ............................................... 773
17.2.8 Internal Bus Reset................................................................................ 774
17.3 Reset Pins ...................................................................................................... 777
17.4 Device Function Select..................................................................................... 778
17.5 Reset Strapping Options................................................................................... 779
18.0 Test Logic Unit and Testability.................................................................................... 782
18.1 Overview ....................................................................................................... 782
18.2 IEEE 1149.1 Standard Test Access Port (TAP) ..................................................... 783
18.2.1 TAP Pin Description............................................................................... 784
18.2.1.1 Test Clock ( TCK ) .................................................................... 784
18.2.1.2 Test Mode Select ( TMS ) .......................................................... 784
18.2.1.3 Test Data Input (TDI).............................................................. 784
18.2.1.4 Test Data Output ( TDO ) .......................................................... 784
18.2.1.5 Asynchronous Reset ( TRST# ) .................................................. 784
18.2.2 TAP Controller...................................................................................... 785
18.2.2.1 Test-Logic-Reset State ............................................................ 786
18.2.2.2 Run-Test/Idle State................................................................. 786
18.2.2.3 Select-DR-Scan State.............................................................. 786
18.2.2.4 Capture-DR State ................................................................... 786
18.2.2.5 Shift-DR State........................................................................ 787
18.2.2.6 Exit1-DR State ....................................................................... 787
18.2.2.7 Pause-DR State ...................................................................... 787
18.2.2.8 Exit2-DR State ....................................................................... 787
18.2.2.9 Update-DR State .................................................................... 787
18.2.2.10Select-IR-Scan State............................................................... 788
18.2.2.11Capture-IR State .................................................................... 788
18.2.2.12Shift-IR State......................................................................... 788
18.2.2.13Exit1-IR State ........................................................................ 788
18.2.2.14Pause-IR State ....................................................................... 788