Outbound vendor defined message payload register, Ovmpr, Address translation unit (pci express)—intel – Intel CONTROLLERS 413808 User Manual

Page 391: Bit default description, Intel

Intel

413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

391

Address Translation Unit (PCI Express)—Intel

413808 and 413812

3.17.114 Outbound Vendor Message Payload Register - OVMPR

The Outbound Vendor Message Payload Register contains the payload data that is used

for the Vendor_Defined Message TLP. A write to this register initiates the

Vendor_Defined Message on the PCI Express Interface. When a zero length payload is

desired, then a write to this register is required to initiate the transaction, but the value

written is ignored.
The 4138xx supports a maximum payload size of 1 DW.
The Vendor_Defined message format is shown in

Note:

This register does not physically exist. It is simply a write port. A read to this register is

not claimed by the ATU and causes a data abort.
This address was chosen to put the data on lane 0 of the 4138xx internal bus.

Table 254. Outbound Vendor Defined Message Payload Register - OVMPR

Bit

Default

Description

31:0

00H

Outbound Vendor_Defined Payload

Reads of this register always return 0.

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

WO = Write Only

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Internal Bus Address Offset

+370H