Intel CONTROLLERS 413808 - Manual (Page 8)

Intel
®
413808 and 413812—Contents
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
8 Order Number: 317805-001US
3.3.5.1 Outbound Configuration Cycle Error Conditions............................253
3.3.5.2 Outbound Configuration Completions with Retry Status (CRS) .......253
3.3.5.3 Outbound PCI Express Message Transactions ..............................254
3.3.5.4 Completion Timeout Mechanism ................................................254
3.4 Big Endian Byte Swapping.................................................................................255
3.4.1 Inbound Byte Swapping.........................................................................255
3.4.2 Outbound Byte Swapping.......................................................................256
3.5 Messaging Unit................................................................................................257
3.6 PCI Express Messages ......................................................................................258
3.7 Expansion ROM Translation Unit.........................................................................260
3.8 ATU Queue Architecture....................................................................................261
3.8.1 Inbound Queues...................................................................................261
3.8.1.1 Inbound Posted Queue Structure...............................................261
3.8.1.2 Inbound Non Posted Queue Structure ........................................262
3.8.1.3 Inbound Completion Queue Structure ........................................262
3.8.1.4 Inbound Transaction Queues Command Translation Summary.......262
3.8.2 Outbound Queues.................................................................................263
3.8.2.1 Relaxed Ordering and No Snoop Outbound Request Attributes.......263
3.8.3 Transaction Ordering.............................................................................264
3.8.3.1 Transaction Ordering Summary.................................................267
3.8.4 Byte Parity Checking and Generation.......................................................268
3.8.4.1 Parity Generation ....................................................................268
3.8.4.2 Parity Checking.......................................................................269
3.8.4.3 Parity Disabled........................................................................269
3.9 ATU Error Conditions........................................................................................270
3.9.1 PCI Express Errors................................................................................271
3.9.1.1 Role Based Error Reporting.......................................................271
3.9.1.2 Malformed Packets ..................................................................272
3.9.1.3 ECRC Check Failed ..................................................................272
3.9.1.4 Unsupported Request...............................................................273
3.9.1.5 Completer Abort......................................................................273
3.9.1.6 Unexpected Completions ..........................................................273
3.9.1.7 Poisoned TLP Received.............................................................274
3.9.1.8 Completion Timeout ................................................................274
3.9.2 Parity Error on the Internal Bus ..............................................................275
3.9.3 ATU Error Summary..............................................................................275
3.10 PCI Express Hot-Plug Support ...........................................................................279
3.11 Reset.............................................................................................................280
3.12 Message-Signaled Interrupts.............................................................................281
3.12.1 Legacy Interrupts .................................................................................281
3.12.2 Internal Interrupts................................................................................281
3.13 Vital Product Data............................................................................................282
3.13.1 Configuring Vital Product Data Operation .................................................282
3.13.2 Accessing Vital Product Data ..................................................................283
3.13.2.1 Reading Vital Product Data .......................................................283
3.13.2.2 Writing Vital Product Data ........................................................284
3.14 Multi-Function Support .....................................................................................285
3.14.1 PCI Express Interface Control Parameters ................................................285
3.14.2 PCI Express Interface Status Reporting....................................................287
3.15 Root Complex Functionality...............................................................................288
3.16 Embedded Bridge Functionality..........................................................................288
3.17 Register Definitions..........................................................................................289
3.17.1 Extended Capabilities Registers ..............................................................290
3.17.2 Internal Bus Addresses..........................................................................293
3.17.3 ATU Vendor ID Register - ATUVID...........................................................297
3.17.4 ATU Device ID Register - ATUDID ...........................................................297