Intel CONTROLLERS 413808 - Manual (Page 315)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 315
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.17.24 ATU Interrupt Line Register - ATUILR
ATU Interrupt Line Register bit definitions adhere to PCI Local Bus Specification,
Revision 2.3. This register identifies the system interrupt controller's interrupt request
lines which connect to the device's PCI interrupt request lines (as specified in the
interrupt pin register).
In a PC environment, for example, the register values and corresponding connections
are:
• 0 (00H) through 15 (0FH) correspond to IRQ0 through IRQ15
• 16 (10H) through 254 (FEH) are reserved
• 255 (FFH) indicates “unknown” or “no connection”
Operating system or device driver can examine each device interrupt pin and interrupt
line register to determine which system interrupt request line the device uses to issue
requests for service.
Table 164. ATU Interrupt Line Register - ATUILR
Bit Default Description
07:00 FFH
Interrupt Assigned - system-assigned value identifies which system interrupt controller interrupt
request line connects to the device's PCI interrupt request lines (as specified in the interrupt pin
register).
A value of FFH signifies “no connection” or “unknown”.
PCI
IOP
Attributes
Attributes
7 4 0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+03CH