10 divisor latch registers, 10divisor latch registers, 459 uart x divisor latch low register - (uxdll) – Intel CONTROLLERS 413808 User Manual

Page 685: 460 uart x divisor latch high register - (uxdlh)

Intel

413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

685

UARTs—Intel

413808 and 413812

13.4.10 Divisor Latch Registers

The description of use for the Divisor Latch Registers are provided in

Section 13.3.5,

Auto-Baud-Rate Detection

an d

Section 13.3.6, Manual Baud Rate Selection

. Refer to

those sections for details on how to program these registers.
Bit DLAB in the LCR register must be set high before the Divisor Latch registers can be

accessed.
A Divisor value of 0 in the Divisor Latch Register is not allowed. A value of 0 has the

affect of disabling the UART. The reset value of the divisor is 02.

Table 459. UART x Divisor Latch Low Register - (UxDLL)

Bit

Default

Description

31:8

00 0000h

Reserved

7:0

02h

Low byte compare value to generate baud rate

Table 460. UART x Divisor Latch High Register - (UxDLH)

Bit

Default

Description

31:8

00 0000h

Reserved

7:0

00h

High byte compare value to generate baud rate

Unit #

Intel XScale

Core internal bus address

+2300H (DLAB=1)

+2340H (DLAB=1)

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible