Intel CONTROLLERS 413808 - Manual (Page 406)

Intel
®
413808 and 413812—Messaging Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
406 Order Number: 317805-001US
4.6 Message-Signaled Interrupts
4.6.1 MSI Capability Structure
When a host processor enables Message-Signaled Interrupts (MSI) on the 4138xx ATU
function, the ATU function (MU) is responsible to signal interrupt to the host via a host
I/O interface write instead of the assertion of the P_INTA# output pin.
The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a states that
“PCI-X devices that generate interrupts are required to support message-signaled
interrupts, as defined by the PCI Local Bus Specification, Revision 2.2 and must support
a 64-bit message address.” “Devices that require interrupts in systems that do not
support message-signaled interrupts, must implement interrupt pins.” Thus, the
4138xx needs to implement both wired and message-signaled interrupt delivery
mechanisms.
In support of MSI, the 4138xx implements the MSI capability structure. The capability
structure includes the “Message Control Register - Message_Control” on page 431 , the
“Message Address Register - Message_Address” on page 432 , the “Message Upper
Address Register - Message_Upper_Address” on page 433 and the “Message Data
Register- Message_Data” on page 434 .
During system initialization, the configuration software for an MSI system reads the
Message Control Register to determine that the 4138xx supports a 64-bit Message
Address, and that it is capable of generating two unique interrupt messages.
After gathering this data from all of the MSI capable devices in the system, the
configuration software decides where to initialize the Message Address and how many
unique messages each MSI capable device is allowed. Then, software writes the
Message Address Registers (and the Message Upper Address Registers when Message
Address is above the 4G address boundary
12
), and the Message Data Register. This
system specified data is used to route the interrupt request message to the appropriate
entry in a host processor Local APIC table.
Configuration of MSI completes with a write to the Message Control Register which
includes an update to the Multiple Message Enable field and the MSI enable bit of each
device. This informs the device how many unique messages (Local APIC table entries)
have been allocated for exclusive use by that device and enable that device for MSI.
Device hardware is required to handle allocation of fewer unique interrupt messages
than requested by the Multiple Message Capable field.
The 4138xx is able to handle generating only one message, even though the device is
capable of generating two unique messages. When two unique messages are enabled,
one message is reserved for Outbound Post Queue Interrupt, the other message
represents all of Outbound Doorbell and Outbound Message Interrupts. When only one
message is enabled, all interrupts are represented by a single message. Interrupt
handler software needs to read the 4138xx Outbound Interrupt Status Register to
determine the cause of the interrupt when more than one source is represented by a
single message.
To signal an Outbound Interrupt with MSI enabled, the 4138xx creates an outbound
write transaction using the Message Address and the Message Data. When two unique
messages are enabled, the lowest order bit of the Message Data is modified by
hardware so that the host processor can distinguish between them.
12.When host software writes the Message Upper address register to a non-zero value, device
hardware uses a write transaction with a Dual Address Cycle (DAC) to present the full 64-bit
address to the bus.