Intel CONTROLLERS 413808 - Manual (Page 624)

Intel
®
413808 and 413812—Interrupt Controller Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
624 Order Number: 317805-001US
10.7.30 Interrupt Priority Register 5 — IPR5
The Interrupt Priority Register 5 is a 32-bit Coprocessor 6 control register used to
assign a priority level to interrupt sources 95 down to 80. The IPR5 control register is
used to assign one of 4 priority levels to each interrupt source independent of the
INTSTR[3:0] registers:
When interrupt vector generation is enabled and there are multiple requests pending
either in the FINTSRC[3:0] or the IINTSRC[3:0] registers, the highest priority vectors
pending for either FIQ or IRQ are presented in the FINTVEC or IINTVEC respectively.
Note: When multiple interrupts at the same priority level are pending for either FIQ or IRQ,
the vector is selected according to a fixed priority based on bit location. Highest order
bit is first.
00
2 —
High Priority
01
2 —
Medium/High Priority
10
2 —
Medium/Low Priority
11
2 —
Low Priority
Table 412. Interrupt Priority Register 5 — IPR5
Bit Default Description
31:30 00
2
SRAM Memory Controller Unit Error Interrupt Priority.
29:28 00
2
South Internal Bus Bridge Error Interrupt Priority.
27:00 00
2
Reserved.
Memory
Coprocessor
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Coprocessor address
CP6, Page 8, Register 5