Intel CONTROLLERS 413808 - Manual (Page 605)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 605
Interrupt Controller Unit—Intel
®
413808 and 413812
10.7.17 IRQ Interrupt Source Register 0 — IINTSRC0
The IRQ Interrupt Source register is a 32-bit Coprocessor 6 control register used to
specify which of 32 interrupts that are steered to the internal IRQ exception are
unmasked by the INTCTL0 register and active. The INTSTR0 control register is used to
steer individual interrupts to the IRQ exception.
The IINTSRC0 register may be used by an Interrupt Service Routine (ISR) to determine
quickly the source of an IRQ interrupt.
Table 399. IRQ Interrupt Source Register 0 — IINTSRC0 (Sheet 1 of 2)
Bit Default Description
31: 0
2
XINT7# Interrupt
0 = Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0
1 = Interrupting and steered to internal IRQ exception and unmasked by INTCTL0
30: 0
2
XINT6# Interrupt
0 = Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0
1 = Interrupting and steered to internal IRQ exception and unmasked by INTCTL0
29: 0
2
XINT5# Interrupt
0 = Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0
1 = Interrupting and steered to internal IRQ exception and unmasked by INTCTL0
28: 0
2
XINT4# Interrupt
0 = Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0
1 = Interrupting and steered to internal IRQ exception and unmasked by INTCTL0
27 0
2
XINT3# Interrupt
0 = Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0
1 = Interrupting and steered to internal IRQ exception and unmasked by INTCTL0
26 0
2
XINT2# Interrupt
0 = Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0
1 = Interrupting and steered to internal IRQ exception and unmasked by INTCTL0
25 0
2
XINT1# Interrupt
0 = Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0
1 = Interrupting and steered to internal IRQ exception and unmasked by INTCTL0
24 0
2
XINT0# Interrupt
0 = Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0
1 = Interrupting and steered to internal IRQ exception and unmasked by INTCTL0
23:19 0
2
Reserved.
18 0
2
Intel XScale ® Processor Cache Interrupt
0 = Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0
1 = Interrupting and steered to internal IRQ exception and unmasked by INTCTL0
17 0
2
Intel XScale ® Processor PMU Interrupt
0 = Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0
1 = Interrupting and steered to internal IRQ exception and unmasked by INTCTL0
Memory
Coprocessor
Attributes
Attributes
28 24 20 16 12 8 4 0 31
ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Coprocessor address
CP6, page 6, Register 0