Intel CONTROLLERS 413808 - Manual (Page 535)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 535
SRAM Memory Controller—Intel
®
413808 and 413812
8.6 Register Definitions
A series of configuration registers control the SMCU. Software can determine the status
of the SMCU by reading the status registers. Table 349 lists all of the SMCU registers
which are detailed further in proceeding sections.
Note: Constant polling of SMCU MMRs can result in inducing long latencies in peripheral unit
SRAM transactions, and therefore may negatively impact performance. Polling of SMCU
MMRs should be avoided.
Table 349. Memory Controller Register
Section, Register Name — Acronym (Page)
Section 8.6.1, “SRAM Base Address Register — SRAMBAR” on page 536
Section 8.6.2, “SRAM Upper Base Address Register — SRAMUBAR” on page 536
Section 8.6.3, “SRAM ECC Control Register — SECR” on page 536
Section 8.6.4, “SRAM ECC Log Register — SELOGR” on page 538
Section 8.6.5, “SRAM ECC Address Register — SEAR” on page 540
Section 8.6.6, “SRAM ECC Context Address Register — SECAR” on page 540
Section 8.6.7, “SRAM ECC Test Register — SECTST” on page 541
Section 8.6.8, “SRAM Parity Control and Status Register — SPARCSR” on page 542
Section 8.6.9, “SRAM Parity Address Register — SPAR” on page 543
Section 8.6.10, “SRAM Parity Upper Address Register — SPUAR” on page 543
Section 8.6.6, “SRAM ECC Context Address Register — SECAR” on page 540
Section 8.6.11, “SRAM Memory Controller Interrupt Status Register — SMCISR” on page 544