Intel CONTROLLERS 413808 - Manual (Page 711)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 711
I 2 C Bus Interface Units—Intel ® 413808 and 413812
14.5.5 Read 2 Bytes as a Master — Send STOP Using the Abort
1. Write IDBR: Target slave address and R/W# bit (1 for read)
2. Write ICR: Set START bit, Clear STOP bit, Disable Arb loss interrupt, Set Transfer
Byte bit to initiate the access
3. Wait for IDBR Transmit Empty interrupt. When interrupt comes.
Read status register: IDBR Transmit Empty (set), Unit Busy (set), R/W# bit (set)
Clear IDBR Transmit Empty bit to clear the interrupt.
4. Read byte 1
Write ICR: Clear START bit, Clear STOP bit, Enable Arb Loss interrupt, Clear
Ack/Nack bit (Ack), Set Transfer Byte bit to initiate the access
5. Wait for Buffer full interrupt.
Read status register: IDBR Receive Full (set), Unit busy (set), R/W# bit (Set),
Ack/Nack bit (Clear)
Clear IDBR Receive Full bit to clear the interrupt.
Read IDBR data.
6. Read byte 2 with Nack (STOP is not set because STOP or Repeated START are
decided on the byte read)
Write ICR: Clear START bit, Clear STOP bit, Enable Arb Loss interrupt, Set Ack/Nack
bit (Nack), Set Transfer Byte bit to initiate the access
7. Wait for Buffer full interrupt.
Read status register: IDBR Receive Full (set), Unit Busy (set), R/W# bit (Set),
Ack/Nack bit (Set)
Clear IDBR Receive Full bit to clear the interrupt.
Read IDBR data.
There are now two options based on the byte read:
• Send a repeated START
• Send a STOP only
Here, a STOP abort is sent.
Note: Had a NACK not been sent, the next transaction must involve another data byte read.
8. Send STOP abort condition. (STOP with no data transfer.)
Write ICR: Set Master abort.