Intel CONTROLLERS 413808 - Manual (Page 269)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 269
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.8.4.2 Parity Checking
On an outbound request, address parity is checked on the address bus A[35:0]. The
parity bits are checked by first bit XORing the address bits shown in Table 133 with the
corresponding address parity bits, and then verifying when the result of each of the
XORed operations are equal to zero. As an example, the parity calculation for the
lowest order byte of the address bus A[7:0] is carried as follows:
Equation 13.PARITY_RESULT = ADDP0 XOR A[0] XOR A[1] XOR A[2] XOR A[3] XOR A[4]
XOR A[5] XOR A[6] XOR A[7]
The parity logic uses the following algorithm. This algorithm logs the error when an
error is detected.
check address parity
if parity is good
done
else {error}
create an error log
Interrupt the core (if enabled)
On an outbound request with data, data parity is checked on the data bus D[127:0].
The parity bits are checked by first bit XORing the data bits shown in Table 133 with the
corresponding data parity bits, and then verifying when the result of each of the XORed
operations is equal to zero. As an example, the parity calculation for the lowest order
byte of the data bus D[7:0] is carried as follows:
Equation 14.PARITY_RESULT = DATAP0 XOR D[0] XOR D[1] XOR D[2] XOR D[3] XOR D[4]
XOR D[5] XOR D[6] XOR D[7] XOR WBE[0]
A non-zero result from the above operation indicates a parity error.
The parity logic uses the following algorithm, and this algorithm logs the error when an
error is detected.
check data parity
if parity is good
done
else {error}
create an error log
Interrupt the core (if enabled)
3.8.4.3 Parity Disabled
When software disables parity, the ATU does generate the parity inbound transactions,
but does not check the parity on outbound transactions.