Intel CONTROLLERS 413808 - Manual (Page 658)

Intel ® 413808 and 413812—SMBus Interface Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
658 Order Number: 317805-001US
12.4.7 SMBus Controller Data Register — SM_DATA
This register is used to read or write data to the desired Configuration Register.
At the completion of a Read command, this register contains the data from the selected
configuration register. For reads the data register always returns 32 bits and is always
aligned on a DWORD boundary.
Before issuing a write command this register should be written with the desired write
data. For a byte, only the D[7:0] data is written to the desired configuration register.
For a word write, only the D[15:0] data is written to the desired configuration register.
The register number must be word aligned for word writes. For a DWORD write, all 32
bits of data are used. The register number must be DWORD aligned.
The Status Register should be checked to make sure that there is not a command
currently in progress, before writing to this register. Writing to this register when the
Busy bit in the Status Register is asserted, has indeterminate effects.
12.4.8 SMBus Controller Status Register — SM_STS
The SM_STS Register provides the status of the internal transaction. For an SMBus read
transaction, the data is preceded by a byte of status.
Table 440. SMBus Controller Data Register — SM_DATA
Bit Reset Description
31:24 00H Byte 3 (B3): Data bits [31:24].
23:16 00H Byte 2 (B2): Data bits [23:16].
15:08 00H Byte 1 (B1): Data bits [15:8].
07:00 00H Byte 0 (B0): Data bits [7:0].
Table 441. SMBus Controller Status Register — SM_STS
Bit Reset Description
07 0 Reserved
06 0 Internal Address Error
05 0 Internal Master Abort
04 000 Internal Target Abort
03:01 0 Reserved
00 000 Successful
Notes:
1. An Address Error is signalled when an address parity is detected. The error is logged in the System Controller.