Intel CONTROLLERS 413808 - Manual (Page 263)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 263
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.8.2 Outbound Queues
The outbound queues of the ATU are used to hold read and write transactions from the
core processor directed at the PCI Express Link. Each ATU outbound queue structure
has a separate read queue, write queue, and address queue. Table 128 contains
information about ATU outbound queues.
The outbound queues are capable of holding outbound memory read, memory write,
I/O read, and I/O write transactions. The type of transaction used is defined by the
internal bus address and the command used on the internal bus. See Section 3.3.2 and
Section 3.3.3 for details on outbound address translation.
When an internal bus agent initiates an outbound write transaction, the address is
entered into the OWADQ (when not full). The data from the internal bus write is then
entered into the OWQ and the transaction is forwarded to the PCI Express Link. When
the write completes (or an error occurs), the address is flushed from the OWADQ. Data
is flushed only for the master abort or target abort cases.
For outbound reads, the address is entered into the OTQ (when not full) and a split
response termination is signaled to the requester on the internal bus. Read data is
fetched and returned to the requester on the internal bus.
3.8.2.1 Relaxed Ordering and No Snoop Outbound Request Attributes
The ATU may set the Relaxed Ordering (RO) and/or the No Snoop (NS) bits for an
outbound request.
For outbound Memory Read and Memory Write requests initiated by the ADMA the
values of the attribute bits are controlled by the ADMA Descriptor Control Word.
For any other outbound requests, the NS and RO attribute bits is set to ‘0’.
Note: When the Enable Relaxed Ordering or Enable No Snoop bits are cleared in the “PCI
Express Device Control Register - PE_DCTL” on page 344 , then the ATU forces the RO
and NS attributes to ‘0’ respectively for all transactions.
Table 128. Outbound Queues
Queue Mnemonic Queue Name
Queue Size
(Bytes)
OPDQ Outbound Posted Data Queue 4 KBytes
OIPHQ Outbound Posted Header Queue 16 Headers
ONPQ Outbound Non Posted Queue 8 Headers a
a. Non Posted request with data (I/O and Configuration Writes) always use the 3DW header. The associated data
is always 1 DW in size and can be stored the 4th DW of the header queue.
OCPLDQ Outbound Completion Data Queue 4 KBytes
OCPLHQ
Outbound Completion Header
Queue
4 Headers