120 pci interface error header log 2 - pie_log2, 121 pci interface error header log - pie_log3, 120pci interface error header log 2 - pie_log2 – Intel CONTROLLERS 413808 User Manual

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Intel

413808 and 413812—Address Translation Unit (PCI Express)

Intel

413808 and 413812 I/O Controllers in TPER Mode

Developer’s Manual

October 2007

396

Order Number: 317805-001US

3.17.120 PCI Interface Error Header Log 2 - PIE_LOG2

Transaction header log for PCI interface errors.

3.17.121 PCI Interface Error Header Log - PIE_LOG3

Transaction header log for PCI interface errors.

Table 260. PCI Interface Error Header Log 2 - PIE_LOG2

Bit

Default

Description

31:0

3rd DWord of the Header for the PCI Express packet in error.

Once an error is logged in this register, it remains locked for further error logging until the time the

software clears the status bit that cause the header log i.e. the error pointer is rearmed to log again.

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Internal Bus Address Offset

+394H

Table 261. PCI Interface Error Header Log - PIE_LOG3

Bit