11 msi inbound message register - mimr, Table 276. msi inbound message register - mimr, 11 msi inbound message register — mimr – Intel CONTROLLERS 413808 User Manual

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Intel

413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

421

Messaging Unit—Intel

413808 and 413812

4.7.11

MSI Inbound Message Register — MIMR

The MSI Inbound Message (MIMR) is a 16-bit data register that can be used to receive

inbound MSI interrupt (Message-Signaled Interrupt) from external PCI devices. When

operating as a Root Complex (ATU-E) or Central Resource (ATU-X) device, an external

PCI device can signal an interrupt by writing the MSI Inbound Message Register. The

MU interprets the data bits of MIMR as follows:

— Bit[15] of MIMR is used to select the Intel XScale

processors to be the target

of the MSI interrupt. For example, the MSI interrupt can be targeted to either

Intel XScale

processor 0 (coreID = 0) or Intel XScale

processor 1 (coreID =

1). Refer to the EI_BS chapter for more details on coreID assignments.

— Bits[14:07] of MIMR are reserved.

Bits[06:00] of MIMR are treated as a vector field which is one-hot decoded and the bits

are posted in Intel XScale

processor co-processor registers. Refer to

Section 4.7.32,

“Inbound MSI Interrupt Pending Register x — IMIPRx”

for more details on IMIPR[0:3].

Table 276. MSI Inbound Message Register - MIMR

Bit

Default

Description

31:16

0000H

Reserved

Core Select Bit - This bit is used to select the Intel XScale

processor

which is the target of the MSI

Interrupt.

0 = Intel XScale

processor

0 (coreID == 0)

1 = Intel XScale

processor

1 (coreID == 1)

14:07

00H

Reserved

06:00

0000000

Interrupt Vector - This bit field is used to generate a one-hot bit which is posted in Intel XScale

processor

co-processor registers (

Section 4.7.32, “Inbound MSI Interrupt Pending Register x

— IMIPRx”

). Each interrupt vector value is associated with one bit in the co-processor registers. For

example, interrupt vector value == 0 is associated with bit 0 of IMIPR0, interrupt vector value == 32 is

associated with bit 0 of IMIPR1, interrupt vector value == 64 is associated with bit 0 of IMIPR2, and so

on. Refer to

Section 4.7.32, “Inbound MSI Interrupt Pending Register x — IMIPRx”

for more

details on IMIPR[0:3].

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

MU/PCI Base Address Offset

MIMR: 0048H

internal bus address offset

MIMR: 4048H