Intel CONTROLLERS 413808 - Manual (Page 659)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 659
UARTs—Intel ® 413808 and 413812
13.0 UARTs
Note: UART0 is owned by the Transport Core. See the System/Software Architecture
Specification for details on how to change this.
This chapter describes the Universal Asynchronous Receiver/Transmitter (UART) serial
ports. The Intel
®
413808 and 413812 I/O Controllers in TPER Mode (4138xx) UARTs
are controlled via programmed I/O through memory-mapped registers.
13.1 Overview
Each asynchronous serial port supports all the functions of 16550 UART. Each UART
performs serial-to-parallel conversion on data characters received from a peripheral
device or a modem and parallel-to-serial conversion on data characters received from
the processor. The processor can read the complete status of a UART at any time during
the functional operation. Available status information includes the type and condition of
the transfer operations being performed by a UART and any error conditions (parity,
overrun, framing, or break interrupt).
Each serial port can operate in either FIFO or non-FIFO mode. In FIFO mode, a 64-byte
transmit FIFO holds data from the processor to be transmitted on the serial link and a
64-byte Receive FIFO buffers data from the serial link until read by the processor.
Each UART includes a programmable baud rate generator which is capable of dividing
the input clock by divisors of 1 to (2
16
–1) and producing a 16X clock to drive the
internal transmitter and receiver logic. Interrupts can be programmed to the user’s
requirements, minimizing the computing required to handle the communications link.
Each UART operates in a polled or an interrupt driven environment which is selected by
software.