Intel CONTROLLERS 413808 - Manual (Page 794)

Intel ® 413808 and 413812—Peripheral Registers
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
794 Order Number: 317805-001US
19.0 Peripheral Registers
This chapter summarizes the registers for the integrated peripherals. Each register is
defined in detail in the corresponding unit chapter.
19.1 Overview
Intel
®
413808 and 413812 I/O Controllers in TPER Mode (4138xx) Peripheral Registers
can be accessed via three methods:
• PCI Configuration Register interface: Is supported by the PCI interface and PCI
Configuration Cycle transaction type.
• Peripheral Memory-Mapped Register (PMMR) interface: Gives software
ability to read and modify internal control registers. These registers are accessed
as a memory-mapped 32-bit register with unique memory address. Access is
accomplished through regular Intel XScale
®
processor memory-format instruction.
• High-performance Intel XScale
®
processor (ARM* architecture compliant)
Coprocessor Register interface (CCR): Gives software ability to read and
modify internal control registers at very low latency as compared to PMMR
interface.
These registers are specific to the 4138xx only. They support the:
Each of these peripherals fully describe the independent functionality of the registers,
control and usage.
Control and status registers for the Intel XScale
®
processor use the CCR interface.
Accesses to coprocessor registers do not generate external bus cycles. See the Intel
®
80200 Processor based on Intel
®
XScale™ Microarchitecture Developer’s Manual
(Order Number: 273411) for a full description of the usage of the coprocessor register
space. For completeness, these registers are included in the tables of registers for the
CCR interface. These registers can only be accessed using the coprocessor instructions.
The PMMR interface provides full accessibility from the ATU, and the Intel XScale
®
processor. The PMMR block can be mapped to any 512-KByte aligned address boundary
using the PMMR Base Address registers. The default starting address of the PMMR block
is 0 FFD8 0000H and cannot be changed.
• I/O Level Control • UART Units
• Internal Bus Bridge Unit • Address Translation Unit (PCI-X and PCI-E)
• SRAM Memory Controller • SRAM DMA Controller Unit
• I
2
C Bus Interface Units • Peripheral Performance Monitoring Unit
• Interrupt Controller Unit • General Purpose I/O Unit
• Messaging Unit • Peripheral Bus Interface Unit
• System Controllers • Intel XScale
®
processor Bus Interface Unit