Intel CONTROLLERS 413808 - Manual (Page 33)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 33
Contents—Intel
®
413808 and 413812
492 PMON Command Register 0-7 - PMON _CMD[0:7]..................................................... 749
493 PMON Event Register 0-7 - PMON _EVR[0:7]............................................................ 753
494 PMON Status Register 0-7 - PMON _STS[0:7]........................................................... 754
495 PMON DATA Register 7-0 - PMON _DATA[7:0] .......................................................... 756
496 Event Selection Code Summary ............................................................................... 757
497 Intel
®
413808 and 413812 I/O Controllers in TPER Mode PMON Clock Events ............... 757
498 Intel
®
413808 and 413812 I/O Controllers PMON Clock Events ................................... 758
499 Intel
®
413808 and 413812 I/O Controllers PMON Threshold Events............................. 758
500 PCI Interface Events............................................................................................... 759
501 PCI Express Interface Summary............................................................................... 760
502 North Internal Bus Source Select Summary ............................................................... 761
503 North Internal Bus Initiator Events ........................................................................... 761
504 South Internal Bus Source Select Summary............................................................... 762
505 South Internal Bus Initiator Events........................................................................... 762
506 PCI Bus Frequency Initialization ............................................................................... 765
507 CR_FREQ[1:0] Encoding ....................................................................................... 765
508 HS_FREQ Encoding ................................................................................................ 766
509 PCI-X Initialization Pattern
1
..................................................................................... 766
510 Secondary Clock Output Control............................................................................... 767
511 Clock Pin Summary ................................................................................................ 769
512 Core Reset Control Bit Locations .............................................................................. 773
513 Internal Bus Reset Control Bit Locations.................................................................... 775
514 Internal Bus Reset Summary ................................................................................... 775
515 Reset Pin Summary................................................................................................ 777
516 TPER Mode Per Function Storage Port Allocation ( CONTROLLER_ONLY# =1) ................ 778
517 Non-TPER Mode Per Function Storage Port Allocation ( CONTROLLER_ONLY# =0) ......... 778
518 Reset Strap Signals ................................................................................................ 780
519 TLU TAP Controller Instruction Set............................................................................ 791
520 IOP Device ID Register Field Definitions ................................................................... 792
521 IOP Device ID Register Settings ............................................................................... 792
522 PMMR Base Address Register (PMMRBAR) Default Value .............................................. 798
523 Local Addresses for Integrated Peripherals ................................................................ 798
524 PBI Base Address Offset.......................................................................................... 801
525 Peripheral Bus Interface Unit ................................................................................... 801
526 SC Base Address Offset........................................................................................... 802
527 System Controller Unit............................................................................................ 802
528 Internal Bus Bridge Base Address Offset.................................................................... 802
529 Internal Bus Bridge ................................................................................................ 802
530 I/O Pad Control Base Address Offset......................................................................... 803
531 I/O Pad Control Unit............................................................................................... 803
532 UART 0-1 Offset..................................................................................................... 804
533 UART.................................................................................................................... 804
534 GPIO Offset........................................................................................................... 805
535 GPIO.................................................................................................................... 805
536 I
2
C 0-2 Offset........................................................................................................ 805
537 I2C Unit................................................................................................................ 805
538 Messaging Unit Offset............................................................................................. 806
539 Messaging Unit ...................................................................................................... 806
540 PMON Unit Base Address Offset. ............................................................................. 808
541 PMON Unit ........................................................................................................... 808
542 PCI Function MMR Locations .................................................................................... 809
543 Intel
®
413808 and 413812 I/O Controllers ATUX Configuration Space Base Address Offset ...
810
544 Address Translation Unit Registers — ATUX ............................................................... 811