Intel CONTROLLERS 413808 - Manual (Page 323)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 323
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.17.35 Inbound ATU Translate Value Register 2 - IATVR2
The Inbound ATU Translate Value Register 2 (IATVR2) in conjunction with the “Inbound
ATU Upper Translate Value Register 2 - IAUTVR2” on page 324 contain bits 35 to 8 of
the internal bus address used to convert PCI Express Link addresses. The converted
address is driven on the internal bus as a result of the Inbound ATU address
translation.
Warning:
When the IABAR2 register’s Memory Space Indicator is set, inbound window 2 will be in
I/O space. In this case, the PCI Local Bus Specification, Revision 2.3 requires that the
IABAR2 request no more than 256 bytes of I/O space. Thus, IALR2 must be set to
FFFF FF00H when the Memory Space Indicator in IABAR2 is set.
Warning:
Although IATVR2[09:08] are programmable bits, hardware does not translate these
bits for PCI windows that are defined to be less than 1-Kbyte. Hardware uses the PCI
Address bits[09:08] as captured on the PCI address bus to drive the internal bus
address[09:08].
Table 175. Inbound ATU Translate Value Register 2 - IATVR2
Bit Default Description
31:08 00000H
Inbound ATU Translation Value 2 - This value represents bits 31 to 8 of the internal bus address used to
convert the PCI address to internal bus addresses. This value must be naturally aligned with the
IABAR2 register’s programmed value (see
Section 3.17.15, “Determining Block Sizes for Base
Address Registers” on page 306
).
07:01 000H Reserved
00 0
Big Endian Byte Swap enable - When set the ATU performs a byte swap on all PCI read/write
transactions through BAR2. When clear, no swap is performed. Refer to Section 3.4, “Big Endian Byte
Swapping” on page 255 for more details.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+05CH