10 bridge error address register - berar, Table 343. bridge error address register - berar, 11 bridge error upper address register - beruar – Intel CONTROLLERS 413808 User Manual

Page 510: 10 bridge error address register — berar, 11 bridge error upper address register — beruar, 343 bridge error address register — berar, 344 bridge error upper address register — beruar, Bridge error, Address register — berar, Bridge error upper address register — beruar

Intel

413808 and 413812—System Controller (SC) and Internal Bus Bridge

Intel

413808 and 413812 I/O Controllers in TPER Mode

Developer’s Manual

October 2007

510

Order Number: 317805-001US

7.5.10

Bridge Error Address Register — BERAR

This register is responsible for logging the lower 32-bit of the 36-bit address of the

bridge request that encountered the error. This register is used in conjunction with the

BERUAR. Refer to

Section 7.5.11, “Bridge Error Upper Address Register — BERUAR” on

page 510

7.5.11

Bridge Error Upper Address Register — BERUAR

This register is responsible for logging the upper 4-bit address of the 36-bit address of

the Bridge request that encountered the error. This register is used in conjunction with

the BERAR (

Section 7.5.10, “Bridge Error Address Register — BERAR” on page 510

Table 343. Bridge Error Address Register — BERAR

Bit

Default

Description

31:00

0000 0000H

Error Address: Stores the lower 32-bit of the 36-bit address of the request that resulted in an error.

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Intel XScale

processor Local Bus Address Offset

+1790H

South XBG

Table 344. Bridge Error Upper Address Register — BERUAR

Bit

Default

Description

31:04

0000 000H

Reserved.

03:00

0000

Error Address: Stores the upper 4 bits of the 36-bit address of the request that resulted in an error.

PCI

IOP