Intel CONTROLLERS 413808 - Manual (Page 72)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
72 Order Number: 317805-001US
2.2.3 Outbound Write Transaction
An outbound write transaction is initiated by the Intel XScale
®
processor
4
or by one of
the ADMA channels and is targeted at a PCI target on the PCI bus. The outbound write
address and write data are propagated from the 4138xx internal bus to a PCI bus
through OWADQ and OWQ, respectively.
The ATUs internal bus target interface claims the write transaction and forwards the
write data through to the targeted PCI bus. The data flow for an outbound write
transaction on the internal bus is summarized in the following statements:
• For Single Address Cycles (SACs), ATU internal bus target interface latches the
address from the internal bus into the OWADQ when that address is inside one of
the outbound translate windows (see Section 2.6 ) and the OWQ is not full.
• For Dual Address Cycles (DACs), ATU internal bus target interface latches address
from the internal bus into the OWADQ when the OWQ is not full and OWADQ is not
full.
• Once outbound address is latched, internal bus target interface stores write data
into the OWQ until the internal bus transaction completes or the reaches a buffer
boundary. The initiator of the transaction is disconnected at an ADB when the
transaction reaches a buffer boundary.
• When the OWADQ is full, the target interface signals a Retry on the internal bus to
the outbound cycle initiator.
• When OWADQ latches the address and corresponding data is latched in a buffer in
OWQ, the outbound cycle is enabled for transmission on the PCI Bus and PCI
interface requests PCI bus.
4. For best performance, the user should designate the two Outbound Memory Windows as
non-cacheable and bufferable from the Intel XScale
®
processor. This assignment enables the
Intel XScale
®
processor to issue multiple outstanding transactions to the Outbound Memory
Windows, thereby, taking full advantage of the ATU outbound queue architecture. However, the
user needs to be aware that the Outbound ATU queue architecture does not maintain strict
ordering between read and write requests as described in Table 14, “ATU Outbound Data Flow
Ordering Rules” on page 88 . In the event that the user requires strict ordering to be maintained.
In the event that the user requires strict ordering to be maintained, the user must change the
designation of this region of memory to be non-cacheable/non-bufferable and enforce the
requirement in software.