Intel CONTROLLERS 413808 - Manual (Page 231)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 231
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
The ATU includes four capability headers that implement Power Management capability
as defined by the PCI Bus Power Management Interface Specification, Revision 1.1,
MSI, MSI-X, and Vital Private Data (VPD) capabilities as defined by PCI Local Bus
Specification, Revision 2.3, and PCI Express capability as defined by PCI Express Base
Specification, Revision 1.0a.
Additionally, the ATU includes three PCI Express Extended capability headers that
implement Advanced Error Handling, Device Serial Number, and Power Budgeting as
defined in the PCI Express Base Specification, Revision 1.0a
The functionality of the ATU is described in the following sections. The ATU has a
memory-mapped register interface that is visible from either the PCI interface, the
internal bus interface, or both.
Figure 22. ATU Block Diagram
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ADDRESS TRANSLATION UNIT
Expansion ROM
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B6332-01