Intel CONTROLLERS 413808 - Manual (Page 378)

Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
378 Order Number: 317805-001US
3.17.99 Outbound Upper 32-bit Memory Window Translate Value
Register 2 - OUMWTVR2
The Outbound Upper 32-bit Memory Window Translate Value Register 2 (OUMWTVR2)
defines the upper 32-bits of address used during a dual address cycle. This enables the
outbound ATU to directly address anywhere within the 64-bit host address space. When
this register is all-zero, then a 3DW header is generated on the PCI bus.
Table 239. Outbound Upper 32-bit Memory Window Translate Value Register 2-
OUMWTVR2
Bit Default Description
31:00 0000 0000H These bits define the upper 32-bits of address.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+31CH