Intel, Bit default description, 0 00h available for vendor definition – Intel CONTROLLERS 413808 User Manual

Page 390

Intel

413808 and 413812—Address Translation Unit (PCI Express)

Intel

413808 and 413812 I/O Controllers in TPER Mode

Developer’s Manual

October 2007

390

Order Number: 317805-001US

3.17.112 Outbound Vendor Message Header Register 2 - OVMHR2

The Outbound Vendor Message Header Registers allow software to create a header that

is used for a Vendor_Defined Message TLP. The OVMHR0-3 registers must be

programmed prior to writing the

Outbound Vendor Defined Message Payload Register -

OVMPR

. A write to the OVMPR initiates the Vendor_Defined Message TLP. When the

payload length is 0, a write to the OVMPR is still required to initiate the TLP but the

data written is ignored. Vendor_Defined message format is shown in

Figure 38

3.17.113 Outbound Vendor Message Header Register 3 - OVMHR3

The Outbound Vendor Message Header Registers allow software to create a header that

is used for a Vendor_Defined Message TLP. The OVMHR0-3 registers must be

programmed prior to writing the

Outbound Vendor Defined Message Payload Register -

OVMPR

. A write to the OVMPR initiates the Vendor_Defined Message TLP. When the

payload length is 0, a write to the OVMPR is still required to initiate the TLP but the

data written is ignored. Vendor_Defined message format is shown in

Figure 38

Table 252. Outbound Vendor Defined Message Header Register 2 - OVMHR2

Bit

Default

Description

31:16

00H

Destination ID - When Type[2:0] indicates Route by ID, this field is Destination ID. Otherwise field is

reserved.

16:0

00H

Vendor ID

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Internal Bus Address Offset

+368H

Table 253. Outbound Vendor Defined Message Header Register 3 - OVMHR3

Bit