6 i2c manual bus control register x - imbcrx, 476 i, C manual bus control register x — imbcrx – Intel CONTROLLERS 413808 User Manual

Page 722: Table 476. i, The i, C bus is hung, the i, Intel, C bus interface units, Bit default description

Intel

413808 and 413812—I

C Bus Interface Units

Intel

413808 and 413812 I/O Controllers in TPER Mode

Developer’s Manual

October 2007

722

Order Number: 317805-001US

14.8.6

C Manual Bus Control Register x — IMBCRx

The I

C Manual Bus Control Register (IMBCRx) can be used to manually release or pull

down the

SCL

and

SDA

pins. The values of these pins are controlled by the IMBCRx

bits 2:1 when bit 0 of the IMBCRx is set. When software determines that the I

C bus is

hung using the

“I2C Bus Monitor Register x — IBMRx” on page 721

, this register may

be used to force the I

C bus out of the hung state.

Note:

When the I

C bus is hung, the I

C unit should also be reset using bit 14 of the

“I2C

Control Register x — ICRx” on page 715

Table 476. I

C Manual Bus Control Register x — IMBCRx

Bit

Default

Description

31:03

Reserved

SDA

Control: When bit 0 of the IMBCRx is set, this bit controls the

SDA

pin.

0 = Pull Down the

SDA

1 = Do Not Pull Down the

SDA

SCL

Control: When bit 0 of the IMBCRx is set, this bit controls the

SCL

pin.

0 = Pull Down the

SCL

1 = Do Not Pull Down the

SCL

Manual I

Pin Control Enable: When set, the

SCL

and

SDA

pins are controlled by bits 1 and 2 of the

IMBCRx register. Otherwise, these pins are controlled by the I

unit’s internal state machine.

PCI

IOP

Attributes

Unit #

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Intel XScale

processor internal bus address

offset

+2518H

+2538H

+2558H