Advanced error control and, Capability register - adverr_ctl, Pci express advanced error header – Intel CONTROLLERS 413808 User Manual
Page 360: Log - adverr_log0, Transaction header log for pci express error, Intel, Bit default description
Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
360
Order Number: 317805-001US
3.17.75 Advanced Error Control and Capability Register - ADVERR_CTL
The register gives the status and control for ECRC checks and also the pointer to the
first uncorrectable error that happened.
Note:
All bits in this register are sticky through reset.
3.17.76 PCI Express Advanced Error Header Log - ADVERR_LOG0
Transaction header log for PCI Express error.
Table 215. Advanced Error Control and Capability Register - ADVERR_CTL
Bit
Default
Description
31:9
0
Preserved.
8
0
ECRC Check Enable - When set enables ECRC checking.
7
1
ECRC Check Capable - Indicates the ATU is capable of checking ECRC.
6
0
ECRC Generation Enable - When set enables ECRC generation.
5
1
ECRC Generation Capable - Indicates the ATU is capable of generating ECRC.
4:0
0 0000
The First Error Pointer - Identifies the bit position of the first error reported in the
Uncorrectable Error Status - ERRUNC_STS
register.
Note:
This register does not update until all bits in the ERRUNC_STS register are cleared.
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
rw
rw
rw
ro
rw
rw
rw
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
S
S
S
S
S
S
S
S
S
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+118H
Table 216. PCI Express Advanced Error Header Log - ADVERR_LOG0
Bit
Default
Description
31:0
0
1st DWord of the Header for the PCI Express packet in error.
Once an error is logged in this register, it remains locked for further error logging until the time the
software clears the status bit that cause the header log i.e. the error pointer is rearmed to log again.
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
S S S S
S S S
S
S S S
S
S S S
S
S S S S
S S S
S
S S S S
S S S
S
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+11CH