13 mu base address register - mubar, Table 278. mu base address register - mubar, 278 mu base address register - mubar – Intel CONTROLLERS 413808 User Manual

Page 423: Table 278, “mu base address register, Mubar

Intel

413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

423

Messaging Unit—Intel

413808 and 413812

4.7.13

MU Base Address Register - MUBAR

MU Base Address Register (MUBAR) contains lower 32-bit of the 36-bit local memory

base address of the MU address space as depicted in

Figure 39

. For example, the MU

address space as viewed from Host I/O Interface. The MU base address is required to

be located on an 8-KByte boundary. The upper four-bits of the MU Base Address are

located in the MU Upper Address Register (MUBAR). Refer to

Section 4.7.14, “MU Upper

Base Address Register - MUUBAR”

. The MU always claim the entire 8 KBytes of the

internal bus address space relative to the MU Base Address Registers. The 8 KBytes

include the MU Registers and MSI-X Data Structures.

Note:

The default values of MUBAR/MUBAR are programmed to match the default values

programmed in the Inbound ATU Translate Value Register 0 - IATVR0/Inbound ATU

Upper Translate Value Register 0 - IAUTVR0. This allows the MU registers to be mapped

in the first 8-KByte of the PCI Window 0 Address space.

Table 278. MU Base Address Register - MUBAR

Bit

Default

Description

31:13

FF000H

MU Base Address - Local memory address of the MU (including MSI-X) registers as viewed from Host I/O

Interface. The MU occupies a 8-KByte space from Host I/O Interface.

12:00

000H

Reserved

PCI

IOP

Attributes

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rv rv rv rv rv rv rv rv rv rv rv rv rv

na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

MUBAR

internal bus address offset

4084H