Intel CONTROLLERS 413808 - Manual (Page 201)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 201
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.14.62 Offset EDh: HS_NXTP - Next Item Pointer
By default, the CompactPCI capability is the last capabilities list for the 4138xx, thus
this register defaults to 00H.
However, this register may be written to 90H prior to host configuration to include the
VPD capability located at off-set 90H.
Warning:
Writing this register to any value other than 00H (default) or 90H is not supported and
may produce unpredictable system behavior.
In order to insure that this register is written prior to host configuration, the 4138xx
must be initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of
PCSR). Typically, the Intel XScale
®
processor would be enabled to boot immediately
following P_RST# assertion in this case (bit 1 of PCSR), as well. Please see Section
2.14.41, “PCI Configuration and Status Register - PCSR” on page 178 for more details
on the 4138xx initialization modes.
Table 89. HS_NXTP - Next Item Pointer
Bit Default Description
07:00 E8H
Next Capabilities Pointer (PTR):
Since the cPCI capabilities are the last in the linked list of extended capabilities in the 4138xx, the
register is set to 00H.
However, this field may be written prior to host configuration with 90H to extend the list to include
the VPD extended capabilities header.
PCI
IOP
Attributes
Attributes
7 4 0
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
Attribute Legend:
RV = Reserved
RW = Read/Write
RO = Read Only
RT = Read/Toggle
RC = Read/Clear
SW = SROM Write
NA = Not Accessible
Register Offset
+0E9H