Intel CONTROLLERS 413808 - Manual (Page 731)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 731
PMON Unit—Intel ® 413808 and 413812
16.3 Definitions
• Duration Count - The counter is incremented for each clock for which the event
signal is asserted logic high.
• Occurrence Count - The counter is incremented each time a rising edge of the
event signal is detected.
• Preconditioning - Altering a signal that represents an event before it is presented to
be counted by the PMON unit. This includes clock crossing logic.
Two optional external pins allow for external visibility and control of the counters. The
output pin signals that one of the following conditions generated an interrupt from any
one of the counters:
• a programmable threshold condition was true,
• a command was triggered to begin
• a counter overflow or underflow occurred.
The figure below represents a single counter block. The muxes, registers, and all other
logic is repeated for each counter that is present. There is a threshold event from each
counter block that feeds into each mux.
Figure 108. Example Block Diagram of Single PMON Counter
B6298-01