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2 address decode blocks, 1 sram memory array space, 2 memory-mapped register space – Intel CONTROLLERS 413808 User Manual

Page 514: 3 north internal bus port address decode, 3 memory transaction queues, 4 configuration registers, 5 sram control block, 1 sram state machine and pipeline queues, Sram memory array space, Memory-mapped register space

2 address decode blocks, 1 sram memory array space, 2 memory-mapped register space | 3 north internal bus port address decode, 3 memory transaction queues, 4 configuration registers, 5 sram control block, 1 sram state machine and pipeline queues, Sram memory array space, Memory-mapped register space | Intel CONTROLLERS 413808 User Manual | Page 514 / 824 2 address decode blocks, 1 sram memory array space, 2 memory-mapped register space | 3 north internal bus port address decode, 3 memory transaction queues, 4 configuration registers, 5 sram control block, 1 sram state machine and pipeline queues, Sram memory array space, Memory-mapped register space | Intel CONTROLLERS 413808 User Manual | Page 514 / 824
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