Cirrus Logic EP93xx - Manual (Page 9)

DS785UM1
©
Copyright 2007 Cirrus Logic, Inc. ix
EP93xx User’s Guide
11.2.4 Host Controller Responsibilities...................................................................................11-8
11.2.4.1 USB States ................................................................................................11-8
11.2.4.2 Frame Management ..................................................................................11-8
11.2.4.3 List Processing ..........................................................................................11-8
11.2.5 USB Host Controller Blocks.........................................................................................11-9
11.2.5.1 AHB Slave .................................................................................................11-9
11.2.5.2 AHB Master ...............................................................................................11-9
11.2.5.3 HCI Slave Block.........................................................................................11-9
11.2.5.4 HCI Master Block.....................................................................................11-10
11.2.5.5 USB State Control ...................................................................................11-10
11.2.5.6 Data FIFO ................................................................................................11-10
11.2.5.7 List Processor ..........................................................................................11-10
11.2.5.8 Root Hub and Host SIE ...........................................................................11-10
11.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-11
Chapter 12. Static Memory Controller ............................................................... 12-1
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1
12.2 Static Memory Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-2
12.3 PCMCIA Interface (EP9315 Processor Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5
12.4 PC Card Memory-Mode Enable Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-8
12.5 PC Card Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-8
12.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-10
12.6.1 Bank Configuration Registers....................................................................................12-10
12.6.2 PCMCIA Configuration Registers (EP9315 Processor Only) ....................................12-13
Chapter 13. SDRAM, SyncROM, and SyncFLASH Controller.......................... 13-1
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1
13.2 Booting from SyncROM or SyncFLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1
13.3 Address Pin Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3
13.4 SDRAM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-4
13.5 Programming Mode Register: SDRAM Or SyncROM Device. . . . . . . . . . . . . . . . . . . . . . .13-6
13.6 SDRAM Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-8
13.6.1 Entering Self Refresh Mode ........................................................................................13-8
13.6.2 Exiting Self Refresh Mode ...........................................................................................13-8
13.7 Programming Registers: SyncFLASH Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-8
13.8 External Synchronous Memory System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-9
13.8.1 Chip Select SDCSN[3:0] Decoding .............................................................................13-9
13.8.2 Address/Data/Control Required by Memory System .................................................13-10
13.9 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-17
Chapter 14. UART1 With HDLC and Modem Control Signals.......................... 14-1
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1
14.2 UART Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1
14.2.1 UART Functional Description ......................................................................................14-2
14.2.1.1 AMBA APB Interface .................................................................................14-2
14.2.1.2 DMA Block .................................................................................................14-2
14.2.1.3 Register Block............................................................................................14-2
14.2.1.4 Baud Rate Generator.................................................................................14-4
14.2.1.5 Transmit FIFO............................................................................................14-4
14.2.1.6 Receive FIFO.............................................................................................14-4
14.2.1.7 Transmit Logic ...........................................................................................14-4
14.2.1.8 Receive Logic ............................................................................................14-4