Cirrus Logic EP93xx User Manual
Page 169
DS785UM1
6-7
Copyright 2007 Cirrus Logic
Vectored Interrupt Controller
EP93xx User’s Guide
6
6
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CLK1HZ
1 Hz clock interrupt. See
.
V_SYNC
Vertical or Composite Sync/Frame Pulse Interrupt. See
"Raster Engine With Analog/LCD Integrated
.
INT_VIDEO_FIFO Video FIFO Interrupt. See
Analog/LCD Integrated Timing and Interface"
INT_SSP1RX
SSP Receive Interrupt. See
.
INT_SSP1TX
SSP Transmit Interrupt. See
.
TC3UI
Timer Counter 3 Underflow Interrupt. This interrupt
becomes active on the next falling edge of the timer
counter 3 clock after the timer counter has under flowed
(reached zero). The interrupt is cleared by writing any
value to the
register. See
.
INT_UART1
UART 1 General Interrupt. This interrupt is active if any
UART1 interrupt is active. Interrupt service routines will
need to read the relevant status bits within UART1 to
determine the source of the interrupt. All these sources
are individually maskable within UART1. See
Chapter 15
,
“UART1”.
SSPINTR
Synchronous Serial Port (SSP) Interrupt. See
.
INT_UART2
UART 2 General Interrupt. This interrupt is active if any
UART2 interrupt is active. Interrupt service routines will
need to read the relevant status bits within UART2 to
determine the source of the interrupt. All these sources
are individually maskable within UART2. See
.
INT_UART3
UART 3 General Interrupt. This interrupt is active if any
UART3 interrupt is active. Interrupt service routines will
need to read the relevant status bits within UART3 to
determine the source of the interrupt. All these sources
are individually maskable within UART3. See
.
USHINTR
USB Host Interrupt. See
Chapter 11
, “USB Host
Controller”.
INT_PME
PME interrupt. See