10 motorola spi format with spo=1, sph=1, 10 motorola spi format with spo=1, sph=1 -9 – Cirrus Logic EP93xx User Manual
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DS785UM1
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Copyright 2007 Cirrus Logic
Synchronous Serial Port
EP93xx User’s Guide
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If the SSP is enabled and there is valid data within the transmit FIFO, the start of 
transmission is signified by the SFRMOUT master signal being driven LOW, which causes 
slave data to be immediately transferred onto the SSPRXD line of the master. The master 
SSPTXD output pad is enabled.
One half period later, valid master data is transferred to the SSPTXD line. Now that both the 
master and slave data have been set, the SCLKOUT master clock pin becomes LOW after 
one further half SCLKOUT period. This means that data is captured on the falling edges and 
is propagated on the rising edges of the SCLKOUT signal.
In the case of a single word transmission, after all bits of the data word are transferred, the 
SFRMOUT line is returned to its idle HIGH state one SCLKOUT period after the last bit has 
been captured.
However, in the case of continuous back-to-back transmissions, the SFRMOUT signal must 
be pulsed HIGH between each data word transfer. This is because the slave select pin 
freezes the data in its serial peripheral register and does not allow it to be altered if the SPH 
bit is logic zero. Therefore the master device must raise the SFRMIN pin of the slave device 
between each data transfer to enable the serial peripheral data write. On completion of the 
continuous transfer, the SFRMOUT pin is returned to its idle state one SCLKOUT period after 
the last bit has been captured.
23.5.10 Motorola SPI Format with SPO=1, SPH=1
The transfer signal sequence for Motorola SPI format with SPO=1, SPH=1 is shown in
, which covers both single and continuous transfers.
Figure 23-8. Motorola SPI Frame Format with SPO=1 and SPH=1
Note:
, Q is an undefined signal.
In this configuration, during idle periods:
•
the SCLKOUT signal is forced HIGH
•
SFRMOUT is forced HIGH
•
the transmit data line SSPTXD is arbitrarily forced LOW
4 to 16 bits
MS B
LS B
LS B
Q
M SB
Q
SSPTXD
SSPOE
SSPRXD
SFRMOUT /
SFRMIN
SCLKOUT /
SCLKIN
