Cirrus Logic EP93xx - Manual (Page 686)

21-30 DS785UM1
Copyright 2007 Cirrus Logic
I 2 S Controller
EP93xx User’s Guide
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Tx1_overflow: when = 1, the tx1 FIFO is full and an attempt has been
made to write data to it by the APB or DMA. This bit is
cleared by writing a 0 to it.
Tx2_overflow: when = 1, the tx2 FIFO is full and an attempt has been
made to write data to it by the APB or DMA. This bit is
cleared by writing a 0 to it.
Rx0_underflow: when = 1, the rx0 FIFO is empty and an attempt has been
made to read data from it by the APB or DMA. This bit is
cleared by writing a 0 to it.
Rx1_underflow: when = 1, the rx1 FIFO is empty and an attempt has been
made to read data from it by the APB or DMA. This bit is
cleared by writing a 0 to it.
Rx2_underflow: when = 1, the rx2 FIFO is empty and an attempt has been
made to read data from it by the APB or DMA. This bit is
cleared by writing a 0 to it.
tx0_fifo_full: when = 1, FIFO is full, otherwise not full
tx0_fifo_empty: when = 1, FIFO is empty, otherwise not empty
tx0_fifo_half_empty:when = 1, FIFO is half empty, otherwise less than half
empty
rx0_fifo_full: when = 1, FIFO is full, otherwise not full
rx0_fifo_empty: when = 1, FIFO is empty, otherwise not empty
rx0_fifo_half_full: when = 1, FIFO is half full, otherwise less than half full
tx1_fifo_full: when = 1, FIFO is full, otherwise not full
tx1_fifo_empty: when = 1, FIFO is empty, otherwise not empty
tx1_fifo_half_empty:when = 1, FIFO is half empty, otherwise less than half
empty
rx1_fifo_full: when = 1, FIFO is full, otherwise not full
rx1_fifo_empty: when = 1, FIFO is empty, otherwise not empty
rx1_fifo_half_full: when = 1, FIFO is half full, otherwise less than half full
tx2_fifo_full: when = 1, FIFO is full, otherwise not full
tx2_fifo_empty: when = 1, FIFO is empty, otherwise not empty
tx2_fifo_half_empty:when = 1, FIFO is half empty, otherwise less than half
empty
rx2_fifo_full: when = 1, FIFO is full, otherwise not full