Cirrus Logic EP93xx - Manual (Page 377)

DS785UM1 9-75
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
Chip Reset:
0x0000_0000
Soft Reset:
Unchanged
Definition:
Receive Buffer Current Address register. The Receive buffer current address
contains the current address being used to transfer receive data. This value
may be useful in debugging.
Bit Descriptions:
RBCA: Receive Buffer Current Address.
RXStsQBAdd
Address:
0x8001_00A0 - Read/Write
Chip Reset:
0x0000_0000
Soft Reset:
Unchanged
Definition:
Receive Status Queue Base Address. The Receive Status Queue Base
Address defines the system memory address of the receive status queue.
This address is used by the MAC to reload the Receive Current Status
Address whenever the end of the status queue is reached. The base address
should be set at initialization time and must be set to a word aligned memory
address.
Bit Descriptions:
RSQBA: Receive Status Queue Base Address.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQBA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQBA