Cirrus Logic EP93xx - Manual (Page 235)

DS785UM1 7-53
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7
7
7
V_CSYNC --> D7 (Smart Panel)
HSYNC --> D6
BLANK --> D5
P17 --> D4
P3 --> D3
P[2:0] --> D[2:0]
SPCLK --> E
A Smart Panel has an integrated controller and frame
buffer. Smart Panel R/W and RS signals must be
implemented via GPIOs and controlled via software.
CCIREN: CCIR Enable - Read/Write
The value written to this bit selects which video output
signals are generated:
0 - Normal signals
1 - CCIR656 YCrCb digital video signals
LCDEN: LCD Enable - Read/Write
The value written to this bit specifies the function of the
signals to the P[16] pin and P[15] pin:
0 - Pixel data bits 16 and 15 are routed to pins P16 and
P15, respectively
1 - XECL and YSCL signals are routed to pins P16 and
P15, respectively. The XECL and YSCL signals are used
to enable LCD drivers and register shifting
ACEN: AC Enable - Read/Write
Writing ACEN = ‘1’ routes an LCD AC Waveform to pin
P17.
0 - Pixel data bit 17 is routed to pin P17
1 - LCD AC Wave Form is routed to pin P17. The
waveform toggles with each new vertical frame.
INVCLK: Invert Pixel Clock - Read/Write
The value written to this bit selects the active edge of
SPCLK on the SPCLK pin:
0 - Pixel data output changes on the rising edge of the
clock on the SPCLK pin