Cirrus Logic EP93xx - Manual (Page 700)

22-12 DS785UM1
Copyright 2007 Cirrus Logic
AC’97 Controller
EP93xx User’s Guide
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TX1: FIFO contains SLOT1 data (only use if sampling rate is
48 kHz). Takes precedence over AC97S1DATA.
TEN: A “1” written to this bit enables the transmit for this FIFO
and enables the PCLK for the respective Channel.
AC97SRx
Address:
AC97SR1 - 0x8088_000C - Read Only
AC97SR2 - 0x8088_002C - Read Only
AC97SR3 - 0x8088_004C - Read Only
AC97SR4 - 0x8088_006C - Read Only
Definition:
Status Registers. The AC’97 Controller status registers are read only registers
that give information about the transmit/receive status of the block. After reset,
the TXFF, RXFF and TXBUSY are “0”, and TXFE and RXFE are “1”.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
TXUE: TX Underrun Error - This bit is set to “1” if an underrun
error has been detected (if data is to be transmitted and
the FIFO is empty).
This bit is cleared to “0” by writing to the AC97DR register.
Note: Bit will only be set if FIFO had been written to at least once in
current data transfer.
RXOE: RX Overrun Error - This bit is set to “1” if an overrun error
has been detected. This bit is set to “1” if data is received
and the FIFO is already full.
This bit is cleared to “0” by reading the AC97DR register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD TXUE RXOE TXBUSY TXFF RXFF TXFE RXFE