Cirrus Logic EP93xx - Manual (Page 60)

2-22 DS785UM1
Copyright 2007 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
2
2
2
0x8008_0008 SMCBCR2
Bank config Register 2 (used to program characteristics of the
SRAM/ROM memory)
N
0x8008_000C SMCBCR3
Bank config Register 3 (used to program characteristics of the
SRAM/ROM memory)
N
0x8008_0010 - 0x8008_0014 Reserved
0x8008_0018 SMCBCR6
Bank config Register 6 (used to program characteristics of the
SRAM/ROM memory)
N
0x8008_001C SMCBCR7
Bank config Register 7 (used to program characteristics of the
SRAM/ROM memory)
N
0x8008_0020 PC1Attribute PC1 Attribute Register
0x8008_0024 PC1Common PC1 Common Register
0x8008_0028 PC1IO PC1 IO Register
0x8008_002C Reserved
0x8008_0030 PC2Attribute PC2 Attribute Register
0x8008_0034 PC2Common PC2 Common Register
0x8008_0038 PC2IO PC2 IO Register
0x8008_003C Reserved
0x8008_0040 PCMCIACtrl PCMCIA Control register
0x8008_0044 - 0x8008_FFFC Reserved
0x8009_xxxx Boot ROM Boot ROM Memory Locations
0x8009_0000 Boot ROM Start N
0x8009_3FFF Boot ROM End N
0x800A_xxxx IDE IDE Control Registers
0x800A_0000 IDECtrl IDE Control Register N
0x800A_0004 IDECfg IDE Configuration Register N
0x800A_0008 IDEMDMAOp IDE MDMA Operation Register N
0x800A_000C IDEUDMAOp IDE UDMA Operation Register N
0x800A_0010 IDEDataOut IDE PIO Data Output Register N
0x800A_0014 IDEDataIn IDE PIO Data Input Register N
0x800A_0018 IDEMDMADataOut IDE MDMA Data Output Register N
0x800A_001C IDEMDMADataIn IDE MDMA Data Input Register N
0x800A_0020 IDEUDMADataOut IDE UDMA Data Output Register N
0x800A_0024 IDEUDMADataIn IDE UDMA Data Input Register N
0x800A_0028 IDEUDMASts IDE UDMA Status Register N
0x800A_002C IDEUDMADebug IDE UDMA Debug Register N
0x800A_0030 IDEUDMAWrBufSts IDE UDMA Write Buffer Status Register N
0x800A_0034 IDEUDMARdBufSts IDE UDMA Read Buffer Status Register N
0x800B_xxxx VIC1 Vectored Interrupt Controller 1 Registers
0x800B_0000 VIC1IRQStatus IRQ status Register N
0x800B_0004 VIC1FIQStatus FIQ status Register N
Table 2-8. Internal Register Map (Continued)
Address Register Name Register Description
SW
Lock