Cirrus Logic EP93xx User Manual

Page 550

14-28

DS785UM1

UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide

CMAS:

Clock Master:
1 - Transmitter and/or receiver use 1x clock generated by
the internal transmitter.
0 - Transmitter and/or receiver use 1x clock generated
externally.

TXCM:

Transmit Clock Mode.
1 - Generate 1x clock when in synchronous HDLC mode
using NRZ encoding.
0 - Do not generate clock.
This bit has no effect unless TXENC is clear and
synchronous HDLC is enabled.

RXCM:

Receive Clock Mode.
1 - Use external 1x clock when in synchronous HDLC
mode using NRZ encoding.
0 - Do not use external clock.
This bit has no effect unless RXENC is clear and
synchronous HDLC is enabled.

TXENC:

Transmit Encoding method.
1 - Use Manchester bit encoding.
0 - Use NRZ bit encoding.
This bit has no effect unless synchronous HDLC is
enabled

RXENC:

Receive Encoding method.
1 - Use Manchester bit encoding.
0 - Use NRZ bit encoding.
This bit has no effect unless synchronous HDLC is
enabled.

SYNC:

Synchronous / Asynchronous HDLC Enable.
0 - Select asynchronous HDLC for TX and RX.
1 - Select synchronous HDLC for TX and RX.

TFCEN:

Transmit Frame Complete Interrupt Enable.
0 - TFC interrupt will not occur.
1 - TFC interrupt will occur whenever TFC bit is set.

TABEN:

Transmit Frame Abort Interrupt Enable.
0 - TAB interrupt will not occur.
1 - TAB interrupt will occur whenever TAB bit is set.

RFCEN:

Receive Frame Complete Interrupt Enable.
0 - RFC interrupt will not occur.
1 - RFC interrupt will occur whenever RAB bit or EOF bit is
set.