Cirrus Logic EP93xx - Manual (Page 125)

DS785UM1 4-7
Copyright 2007 Cirrus Logic
Boot ROM
EP93xx User’s Guide
4
4
4
0x3000_1000
0x6000_0000
0x7000_0000
Code execution will start at address FLASH base + 0x0. The ARM Core will be in SVC mode.
Note: CSn6 is the recommended chip select for Flash when performing an Internal boot. CSn0
must be connected to Flash when performing an External boot.
4.2.4 SDRAM or SyncFLASH Boot
To enable SDRAM or SyncFLASH boot, make sure that the pins are configured for normal
boot mode, as shown in
Figure 4-2 . If booting with SyncFLASH or a 32-bit SDRAM device,
make sure the SDRAM or SyncFLASH word size is correct, as shown in Figure 4-2 . If booting
with a 16-bit SDRAM device, follow the suggested software sequence of commands, as
shown in
Figure 4-2 .
Figure 4-2. Flow chart of Boot Sequence for 16-bit SDRAM Devices
To boot from SDRAM or SyncFLASH, put the ASCII “CRUS” or “SURC” value in the
HeaderID at one of the following locations (this location is Base + 0x0):
0xC000_0000
0xF000_0000
Code execution will start at address Base + 0x4. The ARM Core will be in SVC mode.
Alternatively, to boot from SDRAM or SyncFLASH, put the ASCII “CRUS” or “SURC” value in
the HeaderID at one of the following locations (this is Base + 0x1000):
0xC000_1000
0xF000_1000
Code execution will start at address Base + 0x0. The ARM Core will be in SVC mode.
4.2.5 Synchronous Memory Operation
If running from Synchronous memory, before issuing a software reset, perform this
procedure:
1. Run from SDRAM
2. Perform a software reset (SWRST bit in DEVCFG register)
Boot Internally with Asynchronous Device
Re-configure SDRAM for 16-bit access
Branch to desired SDRAM memory