Cirrus Logic EP93xx - Manual (Page 218)

7-36 DS785UM1
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7
7
7
7.5 Registers
Table 7-12. Raster Engine Register List
Address Name
SW
locked
Type Size Description
0x8003_0000 VLinesTotal Write Read/Write 11 bits Total Number of vertical frame lines
0x8003_0004 VSyncStrtStop Write Read/Write 22 bits Vertical sync pulse setup
0x8003_0008 VActiveStrtStop Write Read/Write 22 bits Vertical active setup
0x8003_0228 VBlankStrtStop Write Read/Write 22 bits Vertical blanking setup
0x8003_000C VClkStrtStop Write Read/Write 22 bits Vertical clock active frame
0x8003_0010 HClkTotal Write Read/Write 11 bits Total Number of horizontal line clocks
0x8003_0014 HSyncStrtStop Write Read/Write 22 bits Horizontal sync pulse setup
0x8003_0018 HActiveStrtStop Write Read/Write 22 bits Horizontal active setup
0x8003_022C HBlankStrtStop Write Read/Write 22 bits Horizontal blanking setup
0x8003_001C HClkStrtStop Write Read/Write 22 bits Horizontal clock active frame
0x8003_0020 Brightness No Read/Write 16 bits PWM brightness control
0x8003_0024 VideoAttribs Write Read/Write 16 bits Video state machine parameters
0x8003_0028 VidScrnPage No Read/Write 32 bits Starting address of video screen
0x8003_002C VidScrnHPage No Read/Write 32 bits
Starting address of video screen half
page
0x8003_0030 ScrnLines No Read/Write 11 bits
Number of active lines scanned to the
screen
0x8003_0034 LineLength No Read/Write 12 bits Length in words of data for lines
0x8003_0038 VLineStep No Read/Write 13 bits Memory step for each line
0x8003_003C LineCarry Write Read/Write 11 bits Horizontal/vertical offset parameter
0x8003_0040 BlinkRate No Read/Write 8 bits Blink counter setup
0x8003_0044 BlinkMask No Read/Write 24 bits
Logic mask applied to pixel to
perform blink operation
0x8003_0048 BlinkPattrn No Read/Write 24 bits
Compare value for determining
blinking pixels.
0x8003_004C PattrnMask No Read/Write 24 bits Mask to limit pattern.
0x8003_0050 BkgrndOffset No Read/Write 24 bits
Background color or blink offset
value.
0x8003_0054 PixelMode No Read/Write 15 bits Pixel mode definition setup register.
0x8003_0058 ParllIfOut No Read/Write 9 bits
Parallel interface write/control
register.
0x8003_005C ParllIfIn No Read/Write 8 + 8 bits Parallel interface read/setup register.