Ideudmadatain, Ideudmasts – Cirrus Logic EP93xx User Manual
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DS785UM1
Copyright 2007 Cirrus Logic
IDE Interface
EP93xx User’s Guide
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addressed and written by the DMA controller. A write by the host during UDMA
data-out operation will erroneously interfere with the UDMA state machine.
Any read will return zero.
Bit Descriptions:
IDEDD:
IDE output data at the tail of the output buffer in UDMA
mode.
IDEUDMADataIn
Address:
0x800A_0024 - Read Only (should be read by the DMA controller only)
Default:
0x0000_0000
Definition:
In UDMA data-in operations, this register contains the data at the head of the
input buffer to be transferred by the DMA controller. The data is read from this
register by the DMA controller. This register should only be addressed and
read by the DMA controller. A read by the host during UDMA data-in operation
will erroneously interfere with the UDMA state machine. Any write is ignored.
Bit Descriptions:
IDEDD:
IDE input data at the head of the input buffer in UDMA
mode.
IDEUDMASts
Address:
0x800A_0028 - Read Only
Default:
0x0000_0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IDEDD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IDEDD
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
N4X
NDI
NDO
RSVD
SBUSY
INTide
DMAide
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
DSDD
DMARQ
DDOE
DM
STOP
HSHD
DA
CS1n
CS0n