Cirrus Logic EP93xx - Manual (Page 85)

DS785UM1 3-15
Copyright 2007 Cirrus Logic
MaverickCrunch Co-Processor
EP93xx User’s Guide
3
3
3
Table 3-5 shows the condition codes, which are bits [31:28] for each instruction format.
The remaining bits in the instruction formats are interpreted as follows:
• opcode1 : MaverickCrunch co-processor-defined opcode
• opcode2 : MaverickCrunch co-processor defined opcode
• CRn : MaverickCrunch co-processor-defined register
• CRd : MaverickCrunch co-processor-defined register
• CRm : MaverickCrunch co-processor-defined register
• Rn : Specifies an ARM base address register. These bits are ignored by the
MaverickCrunch co-processor.
• Rd : Specifies a source or destination ARM register
• cp_num : Co-processor number
• P : Pre-indexing (P=1) or post-indexing (P=0) addressing. This bit is ignored by the
MaverickCrunch co-processor.
• U : Specifies whether the supplied 8-bit offset is added to a base register (U=1) or
subtracted from a base register (U=0). This bit is ignored by the MaverickCrunch co-
processor.
• N : Specifies the width of a data type involved in a move operation. The MaverickCrunch
Table 3-5. Condition Code Definitions
Cond
[31:28]
Mnemonic
Extension
Meaning Status Flag State
0000 EQ Equal Z set
0001 NE Not Equal Z clear
0010 CS/HS Carry Set/Unsigned Higher or Same C set
0011 CC/LO Carry Clear/Unsigned Lower C clear
0100 MI Minus/Negative N set
0101 PL Plus/Positive or Zero N clear
0110 VS Overflow V set
0111 VC No Overflow V clear
1000 HI Unsigned Higher C set and Z clear
1001 LS Unsigned Lower or Same C clear or Z set
1010 GE Signed Greater Than or Equal N set and V set, or N clear and V clear (N = V)
1011 LT Signed Less Than N set and V clear, or N clear and V set (N ! = V)
1100 GT Signed Greater Than Z clear, and either N set and V set, or N clear and V clear (Z = 0, N = V)
1101 LE Signed Less Than or Equal Z set, or N set and V clear, or N clear and V set (Z = 1, N ! = V)
1110 AL Always (unconditional) -
1111 NV Never -