Figure 5-2. clock generation system -6, Figure 5-2 – Cirrus Logic EP93xx User Manual

Page 132

5-6

DS785UM1

System Controller
EP93xx User’s Guide

Figure 5-2. Clock Generation System

5.1.5.2.1 Bus Clock Generation

Figure 5-3

shows the generated clocks: the CPU clock (FCLK), the AHB bus clock (HCLK),

and the APB bus clock (PCLK).

CPU and

Bus Clocks

USB and

FIR Clocks

CPU and

Bus Clocks

32 KHz

Peripheral

Clocks

PLL1

PLL2

Clocks

Audio

Clocks

MIR

Clock

Touch
Clock

Video

Divide

32 KHz Oscillator

WATCH_CLK

14.7456 MHz Oscillator

PLL1 CFG

PLL2 CFG

UARTxCLK

SSPCLK
PWMCLK

Timer Clocks

FCLK

HCLK
PCLK

USBHost48MHz

USBHost12MHz
FIR_CLK

VCLK

SCLK
LRCLK
MCLK

MIR_CLK

KEY_CLK
TOUCH_CLK
ADC_CLK
FILT_CLK

Key

Syscon