Vicxintselect, Vicxintenable – Cirrus Logic EP93xx User Manual
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DS785UM1
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Copyright 2007 Cirrus Logic
Vectored Interrupt Controller
EP93xx User’s Guide
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Definition:
The VICxRawIntr register provides the status of the source interrupts (and
software interrupts) to the interrupt controller.
Bit Descriptions:
RawIntr:
Shows the status of the interrupts before masking by the
enable registers. A “1” indicates that the corresponding
interrupt request is active before masking.
VICxIntSelect
Address:
VIC1IntSelect: 0x800B_000C - Read/Write
VIC2IntSelect: 0x800C_000C - Read/Write
Definition:
Interrupt Select Register. The VICxIntSelect register selects whether the
corresponding interrupt source generates an FIQ or an IRQ interrupt.
Bit Descriptions:
IntSelect:
Selects type of interrupt for interrupt request:
1 = FIQ interrupt
0 = IRQ interrupt.
VICxIntEnable
Address:
VIC1IntEnable: 0x800B_0010 - Read/Write
VIC2IntEnable: 0x800C_0010 - Read/Write
Default: 0x0000_0000
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IntSelect
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IntSelect
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IntEnable
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IntEnable