4 arm co-processor instruction format, 4 arm co-processor instruction format -14 – Cirrus Logic EP93xx User Manual
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Copyright 2007 Cirrus Logic
MaverickCrunch Co-Processor
EP93xx User’s Guide
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3.4 ARM Co-Processor Instruction Format
The ARM V4T architecture defines five ARM co-processor instructions:
•
CDP - Co-processor Data Processing
•
LDC - Load Co-processor
•
STC - Store Co-processor
•
MCR - Move to Co-processor Register from ARM Register
•
MRC - Move to ARM Register from Co-processor Register
The co-processor instruction assembler notation is found in the ARM programming manuals
or the Quick Reference Card. (For additional information, see
) Formats for the above instructions and variants of these
instructions are detailed below.
CDP (Co-Processor Data Processing) Instruction Format
LDC (Load Co-Processor) Instruction Format
STC (Store Co-Processor) Instruction Format
MCR (Move to Co-Processor from ARM Register) Instruction Format
MRC (Move to ARM Register from Co-Processor) Instruction Format
31
28 27
24 23
20 19
16 15
12 11
8
7
5
4
3
0
cond
1110
opcode1
CRn
CRd
cp num
opcode2
0
CRm
31
28 27
25 24 23 22 21 20 19
16 15
12 11
8
7
0
cond
110
P
U
N
W
1
Rn
CRd
cp num
offset
31
28 27
25 24 23 22 21 20 19
16 15
12 11
8
7
0
cond
110
P
U
N
W
0
Rn
CRd
cp num
offset
31
28 27
24 23
21 20 19
16 15
12 11
8
7
5
4
3
0
cond
1110
opcode1
0
CRn
Rd
cp num
opcode2
1
CRm
31
28 27
24 23
21 20 19
16 15
12 11
8
7
5
4
3
0
cond
1110
opcode1
1
CRn
Rd
cp num
opcode2
1
CRm