Cirrus Logic EP93xx - Manual (Page 415)

DS785UM1 10-21
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
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10.2.2 Internal M2P/P2M Channel Register Map
The DMA Memory Map above includes the base address mapping for the channel registers
for each of the 10 M2P/P2M channels that are shown in the following table, the Internal
M2P/P2M Channel Register Map. This mapping is common for each channel thus offset
addresses from the bases in
Table 10-3 are shown in Table 10-4 .
Note:See Table 10-3 for Channel Base Addresses
Note:* - write this location once to clear the interrupt (see Interrupt register description
for which bits this rule applies to).
0x8000_0340 -> 0x8000_037C M2P Channel 8 Registers (Tx) 0x8000_0340
0x8000_0380
DMA Channel Arbitration
register
0x8000_03C0 DMA Global Interrupt register
0x8000_03C4 -> 0x8000_FFFC Not Used 0x8000_03C4
Table 10-4. Internal M2P/P2M Channel Register Map
Offset
Register
Name
Access Bits Reset Value
Channel Base Address + 0x0000 “CONTROL” R/W 6 0
Channel Base Address + 0x0004 “INTERRUPT” R/W TC * 3 0
Channel Base Address + 0x0008 “PPALLOC” R/W 4
Channel dependant
(see register description)
Channel Base Address + 0x000C “STATUS” RO 8 0
Channel Base Address + 0x0010 Reserved
Channel Base Address + 0x0014 “REMAIN” RO 16 0
Channel Base Address + 0x0018 Reserved
Channel Base Address + 0x001C Reserved
Channel Base Address + 0x0020 “MAXCNTx” R/W 16 0
Channel Base Address + 0x0024 “BASEx” R/W 32 0
Channel Base Address + 0x0028 “CURRENTx” RO 32 0
Channel Base Address + 0x002C Reserved
Channel Base Address + 0x0030 “MAXCNTx” R/W 16 0
Channel Base Address + 0x0034 “BASEx” R/W 32 0
Channel Base Address + 0x0038 “CURRENTx” RO 32 0
Channel Base Address + 0x003C Reserved
Table 10-3. DMA Memory Map
ARM920T Address Description Channel Base Address